The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistor devices). Such a transistor device typically includes a gate electrode as a control electrode that is formed overlying a semiconductor substrate and spaced-apart source and drain regions that are formed within the semiconductor substrate and between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductor substrate between the source and drain regions and beneath the gate electrode.
The MOS transistor device is accessed via conductive contacts typically formed on the source and drain regions between the gate electrodes of MOS transistor devices. The conductive contacts are usually formed by siliciding a metal on the source/drain regions, depositing an insulating layer over the silicided source/drain regions, and then etching a contact opening in the insulating layer. A thin barrier layer, typically of titanium nitride and/or other metals and alloys, is deposited in the contact opening and the opening then is filled by a chemical vapor deposited layer of tungsten.
At reduced technology nodes, more and more circuitry is incorporated on a single integrated circuit chip and the sizes of each individual device in the circuit and the spacing between the devices decrease. However, one of the limiting factors in the continued shrinking of integrated semiconductor devices is the resistance of contacts to doped regions such as the source and drain regions. As device sizes decrease, the width of contacts decreases. As the width of the contacts decreases, the resistance of the contacts becomes increasingly larger. In turn, as the resistance of the contacts increases, the drive current of the devices decreases, thus adversely affecting device performance. Therefore, the importance of reducing contact resistance at source/drain regions is amplified at reduced technology nodes.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that exhibit lower contact resistance. In addition, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that utilize a single metal layer to form contact interfaces with source/drain regions in both PFET areas and NFET areas. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.